# Solver Notes

## Formula Notes

The target family is a feed-forward Boolean circuit encoded as truth-table
blocks. For a gate with `fanin = a` and `fanout = b`, each gate contributes
`2^a * (2^b - 1)` clauses of length `a + b`: for every input tuple, all
non-selected output tuples are forbidden. The single missing output tuple is
the gate table value.

The visible train split matches these shapes:

- `4 -> 4` gates with 48 primary inputs and 64 fixed final outputs.
- `6 -> 6` gates with 32 primary inputs and either 32 or 64 fixed outputs.
- `7 -> 7` gates with 32 or 48 primary inputs and 24 or 32 fixed outputs.
- `8 -> 5` gates with 64 primary inputs and 64 fixed outputs.
- Small examples are the same encoding with 8 primary inputs.

The solver must not depend on comments or filenames. It infers the shape from
the header, non-unit clause length, unit count, and divisibility by the gate
block size. Gate outputs are checked as consecutive variables after the primary
input prefix.

## Techniques Used

- Reconstruct fanin, fanout, primary input count, gate wiring, and every gate
  truth table by finding the one missing forbidden output tuple per input row.
- Compute the structural primary-input support of the fixed output units. When
  that support is small and the gate-count/product is bounded, run a two-thread
  AVX-512 byte-lane enumerator over primary assignments. Each SIMD lane carries
  one assignment, arbitrary lookup tables are evaluated with `vpermb`, and a
  successful primary assignment is scalar-forward-filled into a complete CNF
  model. The normal support cap is 30 bits; `8`-input circuits over at most 32
  primaries are allowed up to 32 bits because broker feedback exposed a
  `32in32out 8->6` case that otherwise times out in the CSP fallback.
- Enforce occurrence-queued generalized arc consistency over each recovered
  gate: compatible input rows are enumerated, and any input or output bit
  common to all rows is assigned. Assignments only rescan gates that mention
  the changed variable.
- Branch on the gate with the fewest compatible rows, assigning a complete gate
  row and recursively propagating.
- Score candidate rows with one-step propagation lookahead so branches that
  force more structure are tried earlier.
- Before returning SAT, reopen the original DIMACS file and verify every clause
  against the complete assignment.

## Remaining Things To Try

- Add stronger conflict learning at the gate-CSP level for wide-support cases
  such as the `8->5` seed and large `4->4` seeds.
- Explore a dynamic-programming or cutset method over the generator's distance
  window. The support sizes are much smaller than the full variable count, but
  still too large for direct bitmask DP.
- Improve branching for non-bijective gates by reasoning over output preimage
  multiplicities instead of only row count.

## Known Limitations

- UNSAT is not claimed; unsupported structures and unfinished searches return
  `UNKNOWN`.
- The solver assumes the table clauses for each gate are contiguous and the
  gate output variables are consecutive, which is true for the observed family.
- The AVX-512 primary enumerator is deliberately gated by recovered structural
  support and a vector-gate-evaluation budget. Wider support still uses the
  older gate-CSP DFS.
- Inherited parent provenance: parent SHA
  `445b8a1a6b2b73fbc7435b280a36d90c5fbb192f87d644ba79d020d1ffca8e26`,
  parent solver `lookup-circuit-csp-v1`, parent family `random-circuits`,
  parent eval `eval_20260506T235529Z_a9b42749`, parent score val solved 3/4
  with PAR-2 320.94s.

## Changelog

- Initial scaffold replaced with a C++ detector and direct circuit-CSP solver.
- Added independent DIMACS model verification before emitting `SATISFIABLE`.
- Added candidate branch scoring via propagation lookahead.
- Tested visible train instances: solved examples, representative `4->4`,
  `6->6`, `7->7`, and `8->5` cases; documented current hard seeds.
- Updated `meta.json` and this notebook before broker submission.
- Replaced full propagation rescans with an occurrence-driven gate queue. This
  reduced local time for the 800-gate `4->4` seed from 117s to 5s, the
  1000-gate `4->4` seed from `UNKNOWN` to 31s, and the `8->5` seed from 336s
  to 135s.
- Added a conservative AVX-512 primary-support enumerator for small recovered
  supports. It solves the formerly visible hard `32in64out 6->6` seed in about
  1.5s locally, and also accelerates small-support `6->6`/`7->7` cases while
  leaving wide-support instances on the existing CSP DFS path.
- Tried enabling the existing stochastic local-repair routine for the `8->5`
  case; it failed to find a model within a 60s trial and slowed the total run,
  so the call was not kept.
- Broker run `eval_20260510T024505Z_e6c4fcc5` solved 16 train instances and
  returned one `UNKNOWN`: `32in32out_with_64gates_8in6out_dist128_seed2`.
  Widened the AVX-512 enumerator support cap to 32 bits for 8-input circuits
  with at most 32 primaries to target that family member.
